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march 2015 d ocid026736 rev 2 1 / 37 this is information on a product in full production. www.st.com lnbh25s lnb supply and control ic with step - up and i2c interface datasheet - production data fe atures ? complete interface between lnb and i2c bus ? built - in dc - dc converter for single 12 v supply operation and high efficiency (typ. 93% @ 0.5 a) ? selectable output current limit b y external resistor ? compliant with main satellite receiver output voltage specifications (15 programmable levels) ? accurate built - in 22 khz tone generator suits widely accepted standards ? 22 khz tone waveform integrity guaranteed at no - load condition ? low drop post regulator and high efficiency step - up pwm with integrated power nmos allowing low power losses ? lpm function (low power mode) to reduce dissipation ? overload and overtemperature internal protections with i2c diagnostic bits ? lnb short - circuit dy namic protection ? +/ - 4 kv esd tolerant on output power pins applications ? stb satellite receivers ? tv satellite receivers ? pc card satellite receivers description intended for analog and digital satellite receivers/sat - tv and sat - pc cards, the lnbh25s is a monolithic voltage regulator and interface ic, assembled in qfn24l (4x4 mm) specifically designed to provide 13/18 v power supply and 22 khz tone signaling to the lnb down - converter in the antenna dish or to the multi - switch box. in this application field, it offers a complete solution with extremely low component count and low power dissipation togeth er with a simple design and i2c standard interface. table 1: device summary order code package packing LNBH25SPQR qfn24l (4x4) tape and reel
contents lnbh25s 2 / 37 docid026736 rev 2 contents 1 block diagram ................................ ................................ .................. 6 2 application information ................................ ................................ .. 7 2.1 diseqc data encoding (dsqin p in) ................................ ................. 7 2.2 data encoding by external 22 khz tone ttl signal ........................... 7 2.3 data encoding by external diseqc envelope control through the d sqin pin ................................ ................................ ................................ ...... 8 2.4 lpm (low power mode) ................................ ................................ ..... 8 2.5 diseqc 2.0 implementation ................................ .............................. 8 2.6 output current limit selection ................................ ............................. 9 2.7 output voltage selection ................................ ................................ .... 9 2.8 diagnostic and protection functions ................................ .................. 9 2.9 surge protections and tvs diodes ................................ .................... 9 2.10 flt (fault flag) ................................ ................................ ................. 10 2.11 vmon (o utput voltage diagnostic) ................................ .................. 10 2.12 tmon (22 khz tone diagnostic) ................................ ...................... 10 2.13 tdet (22 khz tone detection) ................................ ......................... 10 2.14 imon (minimum output current diagnostic) ................................ ..... 11 2.15 pdo (overcurrent detection on output pull - down stage) ................. 1 1 2.16 power - on i2c interface reset and undervoltage lockout .................. 11 2.17 png (input voltage minimum detection) ................................ .......... 11 2.18 isw (inductor switching current limit) ................................ .............. 11 2.19 comp (boost capacitors and inductor) ................................ ........... 11 2.20 olf (overcurrent and short - c ircuit protection and diagnostic) ........ 12 2.21 otf (thermal protection and diagnostic) ................................ ......... 12 3 pin configuration ................................ ................................ ........... 13 4 maximum ratings ................................ ................................ ........... 15 5 typical application circuits ................................ ........................... 16 6 i2c bus interface ................................ ................................ ............ 19 6.1 data validity ................................ ................................ ..................... 19 6.2 start and stop condition ................................ ................................ .. 19 6.3 byte format ................................ ................................ ...................... 19 6.4 acknowledge ................................ ................................ ................... 19
lnbh25s contents docid026736 rev 2 3 / 37 6.5 transmission without acknowledge ................................ ................. 19 7 i 2c interface protocol ................................ ................................ .... 21 7.1 write mode transmission ................................ ................................ . 21 7.2 read mode transmission ................................ ................................ 22 7.3 data registers ................................ ................................ .................. 23 7.4 status registers ................................ ................................ ............... 26 8 electrical characteristics ................................ .............................. 28 9 package information ................................ ................................ ..... 33 9.1 qfn24l (4x4 mm) package information ................................ ......... 34 10 revision history ................................ ................................ ............ 36
list of tables lnbh25s 4 / 37 docid026736 rev 2 list of tables table 1: device summary ................................ ................................ ................................ ........................... 1 table 2: pin description ................................ ................................ ................................ ............................ 13 table 3: absolute maximum ratings ................................ ................................ ................................ ......... 15 table 4: thermal data ................................ ................................ ................................ ............................... 15 table 5: diseqc 1.x bil l of material ................................ ................................ ................................ .......... 16 table 6: diseqc 2.x bill of material ................................ ................................ ................................ .......... 17 table 7: data 1 (read/write register. register address = 0x2) ................................ ................................ . 23 table 8: data 2 (read/write register. register address = 0x3) ................................ ................................ . 23 table 9: data 3 (read/write register. register address = 0x4) ................................ ................................ . 24 table 10: data 4 (read/write register. register address = 0x5) ................................ ............................... 24 table 11: status 1 (read register. register address = 0x0) ................................ ................................ ..... 26 table 12: status 2 (read register. register address = 0x1) ................................ ................................ ..... 27 table 13: electrical characteristics ................................ ................................ ................................ ........... 28 table 14: output voltage selection table (data1 register, write mode) ................................ ..................... 30 table 15: i2c electrical characteristics ................................ ................................ ................................ ...... 30 table 16: address pin characteristics ................................ ................................ ................................ ....... 30 table 17: output voltage diagnostic (vmon bit, status 1 register) characteristics ................................ .. 31 table 18: output current diagnostic (imon bit, status 2 register) characteristics ................................ .... 31 table 19: 22 khz tone diagnostic (tmon bit, status 2 register) characteristics ................................ ....... 32 table 20: qfn24l (4x4 mm) mechanical data ................................ ................................ ......................... 35 table 21: document revision history ................................ ................................ ................................ ........ 36
lnbh25s list of figures docid026736 rev 2 5 / 37 list of figu res figure 1: block diagram ................................ ................................ ................................ .............................. 6 figure 2: tone enable and disable timing (using external waveform) ................................ ........................ 8 figure 3: tone enable and disable timing (using envelope signal) ................................ ............................ 8 figure 4: surge protection circuit ................................ ................................ ................................ .............. 10 figure 5: pin connection (top view) ................................ ................................ ................................ .......... 13 figure 6: diseqc 1.x application circuit ................................ ................................ ................................ ... 16 figure 7: diseqc 2.x application circui t ................................ ................................ ................................ ... 17 figure 8: data validity on the i2c bus ................................ ................................ ................................ ....... 20 figure 9: timing diagram of i2c bus ................................ ................................ ................................ ......... 20 figure 10: acknowledge on the i2c bus ................................ ................................ ................................ .... 20 figure 11: example of writing procedure starting with first data address 0x2 ................................ ......... 21 figure 12: example of reading procedure starting with first status address 0x0 ................................ ..... 22 figure 13: qfn24l (4x4 mm) package outline ................................ ................................ ........................ 34 figure 14: qfn24l (4x4 mm) recommended footprint ................................ ................................ ............. 35
block diagram lnbh25s 6 / 37 docid026736 rev 2 1 block diagram figure 1 : block diagram
lnbh25s application information docid026736 rev 2 7 / 37 2 applicat ion information this ic has a built - in dc - dc step - up converter that, from a single source (8 v to 16 v), generates voltages (v up ) which let the integrated ldo post - r egulator (generating13 v/18 v lnb output voltages plus 22 khz diseqc? tone) work with a minimum dissipated power of 0.5 w typ. @ 500 ma load (the ldo drop voltage is internally kept at v up - v out = 1 v typ.). the ldo power dissipation can be reduced when 22 khz tone output is disabled by setting the lpm bit to 1 see section 2.4: "lpm (low power mode)" . the ic is also provided with an undervoltage lockout circuit that disables the whole circuit when the supplied v cc drops bel ow a fixed threshold (4.7 v typ.). the step - up converter soft - start function reduces the inrush current during startup. ss time is internally fixed at 4 ms typ. to switch from 0 to 13 v and 6 ms typ. switch from 0 to 18 v. 2.1 diseqc data encoding (dsqin pin) the internal 22 khz tone generator is factory trimmed in accordance with diseqc standards, and can be active in 3 different ways: 1. by an external 22 khz sour ce diseqc data connected to the dsqin logic pin (ttl compatible). in this case i2c tone control bits have to be set: extm = ten = 1. 2. by an external diseqc data envelope source connected to the dsqin logic pin. in this case i2c tone control bits must be se t: extm = 0 and ten = 1. 3. through ten i2c bit if the 22 khz presence is requested in continuous mode. in this case the dsqin ttl pin must be pulled high and extm bit is set to 0. each of the above solutions requires that during the 22 khz tone activatio n and/or diseqc data transmission, the lpm bit has to be set to 0 see section 2.4: "lpm (low power mode)" . 2.2 data encoding by external 22 khz tone ttl signal in order to improve design flexibility, an external tone signal can be input on the dsqin pin by setting the extm bit to 1. the dsqin is a logic input pin, which activates the 22 khz tone on vout pin, by using the lnbh25s integrated tone generator. the output tone waveforms are internally controlled by the lnbh25s tone generator in terms of rise/fall time and tone amplitude, while, the external 22 khz signal on the dsqin pin is used to define the freque ncy and the duty cycle of the output tone. a ttl compatible 22 khz signal is required for the proper control of the dsqin pin function. before sending the ttl signal to the dsqin pin, the extm and ten bits have to be previously set to 1. as soon as the d sqin internal circuit detects the 22 khz ttl external signal code, the lnbh25s activates the 22 khz tone on the v out output with about 1 s delay from ttl signal activation, and it stops with about 60 s delay after the 22 khz ttl signal on dsqin has expir ed, refer to figure 2: "tone enable and disable timing (using external waveform)" .
application information lnbh25s 8 / 37 docid026736 rev 2 figure 2 : tone enable and disable timing (using external waveform) 2.3 data encoding by external diseqc envelope con trol through the dsqin pin if an external diseqc envelope source is available, the internal 22 khz generator can be activ e during the tone transmission by connecting the diseqc envelope source to the dsqin pin. in this case the i2c tone control bits must be set: extm = 0 and ten = 1. in this manner, the internal 22 khz signal is superimposed to the v out dc voltage to g enerate the lnb output 22 khz tone. during the period in which the dsqin is kept high, the internal control circuit activates the 22 khz tone output. the 22 khz tone on the vout pin is active with about 6 s delay from the dsqin ttl signal rising edge, and it stops with a delay time in the range from 15 s to 60 s after the 22 khz ttl signal on dsqin has expired, refer to figure 3: "tone enable and disable timing (using envelope signal)" . figure 3 : tone enable and disable timing (using envelope signal) 2.4 lpm (low power mode) in order to reduce the total power loss, the lnbh25s is provided with the lpm i2c bit tha t can be activ e (lpm=1) in applications where the 22 khz tone can be disabled for long periods . the lpm bit can be set to 1 when the diseqc data transmission is not requested (no 22 khz tone output is present); the drop voltage across the integrated ldo regulator (v up - v out ) is reduced to 0.6 v typ. and, consequently, the power loss inside the lnbh25s linear regulator is reduced as well. for example: at 500 ma load, lpm=1 allowing a minimum ldo dissipated power of 0.3 w typ. it is recommended to set the lp m bit to 0 before starting the 22 khz diseqc data transmission; at this condition the drop voltage across the ldo is kept to 1 v typ. lpm=0 if the lpm function is not used. 2.5 diseqc 2.0 implementation the built - in 22 khz tone detector completes the fully bi - directional diseqc 2.0 interfacing. the input pin (detin) has to be ac coupled to the diseqc bus, and extracted pwk data is available on the dsqout pin. to com ply with the bi - directional diseqc 2.0 bus hardware requirements, an output rl filter is needed. in order to avoid 22 khz waveform ~ 6 s 15 s ~ 60 s d s q i n t on e o u t pu t gipg090714 1 158lm
lnbh25s application information docid026736 rev 2 9 / 37 distortion during tone transmission, the lnbh25s is provided with the bpsw pin to be connected to an external transistor, whi ch allows the output rl filter to be bypassed in diseqc 2.x applications while in transmission mode. before starting tone transmission, ten bit has to be set to 1 and after ending tone transmission, ten bit has to be set to 0. 2.6 output current limit sele ction the linear regulator current limit threshold can be set by an external resistor connected to the isel pin. the resistor value defines the output curre nt limit by the equation: with iset=0 with iset=1 see iset bit description in table 9: "data 3 (read/write register. register address = 0x4)" , where rsel is the resistor connected between isel and gnd expressed in k an d i lim (typ.) is the typical current limit threshold expressed in ma. i lim can be set up to 1 a. 2.7 output voltage selection the linear regulator output voltage level can be easily programmed in order to accomplish application specific requirements, using 4 bits of an internal data 1 register, see section 7.3: "data registers" and table 14: "output voltag e selection table (data1 register, write mode)" for exact programmable values. register writing is accessible via i2c bus. 2.8 diagnostic and protection functions the lnbh25s has 8 diagnostic internal functions provided by i2c bus, by reading 8 bits on two status registers (in read mode). all the diagnostic bits are, in normal operation (that is no failure detected), set to low. two diagnostic bits are ded icated to the overtemperature and overload protection status (otf and olf) while the remaining 6 bits are dedicated to the output voltage level (vmon), to 22 khz tone characteristics (tmon), to the minimum load current (imon), to external voltage source pr esence on the vout pin (pdo), to the input voltage power not good function (png) and to the 22 khz tone presence on the detin pin (tdet). once the olf (or otf or png) bit is activ e (set to 1), it is latched to 1 until relevant cause is removed and a ne w register reading operation is performed. 2.9 surge protections and tvs diodes the lnbh25s device is directly connected to the antenna cable in a set - top box . atmospheric phenomenon can cause high voltage discharges on the antenna cable causing damage to the attached devices. surge pulses occur due to direct or indirect lightning strikes to an external (outdoor) circuit. this leads to currents or electromagnet ic fields causing high voltage or current transients. transient voltage suppressor (tvs) devices are usually placed, as shown in the following schematic, to protect the stb output circuits where the lnbh25s and other devices are electrically connected to t he antenna cable. i lim (typ.) = 13915 rse l 1. 11 1 i lim (typ.) = 6808 rse l 1.068
application information lnbh25s 10 / 37 docid026736 rev 2 figure 4 : surge protection circuit for this purpose, the use of the lnbtvsxx surge protection diodes specifically designed by st is recommended. the selection of the lnbtvsxx diodes should be based on the maximu m peak power dissipation supported by the diode (see the lnbtvs datasheet for further details). 2.10 flt (fault flag) in order to get an immediate feedback on diagnostic status , the lnbh25s is equipped with a dedicated fault flag pin (flt). in case of overload (olf bit=1) or overheating (otf bit=1) or if power no good (png bit=1) condition is detected, the flt pin (open drain output) is set to low and is kept low until the rel evant activating diagnostic bit is cleared. diagnostic bits: olf, otf and png, once activated, are kept latched to 1 until the root cause is removed and a new register reading operation is performed by the microprocessor. the flt pin has to be connected to a positive voltage (5 v max.) by a pull - up resistor. 2.11 vmon (output voltage diagnostic) when the device output voltage is activ e (v out pin), its value is internally monitored and, as long as the output voltage level is below the guaranteed limits, vmon i2c bit is set to 1. see table 17: "output voltage diagnostic (vmon bit, status 1 register) characteristics" for more deta ils. 2.12 tmon (22 khz tone diagnostic) the 22 khz tone can be internally detected and monitored if detin pin is connected to the lnb output bus, see typical appli cation circuit in figure 7: "diseqc 2.x application circuit" , through a decoupling capacitor. the tone diagnostic function is provided with tmon i2c bit. if the 22 khz tone amplitude and/or the tone frequency is out of the guaranteed limits, see table 19: "22 khz tone diagnostic (tmon bit, status 2 register) characteristics" , tmon i2c bit is set to 1. 2.13 tdet (22 khz tone detection) when a 22 khz tone presence is detected on detin pin, tdet i2c bit is set to 1.
lnbh25s application information docid026736 rev 2 11 / 37 2.14 imon (minimum output current diagnostic) in order to detect the output load absence (no lnb connected on the bus or cable not connected to the ird) the lnbh25s is provided with a minimum output current flag by the imon i2c bit, accessible in read mode, which is set to 1 if the out put current is lower than 12 ma (typ.). imon function should be used with the 22 khz tone transmission deactivated, otherwise the imon bit could be set to 0 even if the output current is below the minimum current threshold. to activate imon diagnostic fu nction, the en_imon i2c bit has to be set to 1 in the data 4 register. as soon as the imon function is active by en_imon=1, v out rises 21 v (typ.) on the vsel bit setting. this operation is applied to be sure that the lnbh25s output has the higher voltag e in the lnb bus. do not use this function in an application environment where 21 v voltage level is not supported by other peripherals connected to the lnb bus. 2.15 pdo (overcurrent detection on output pull - down stage) when an overcurrent occurs on the pull - down output stage due to an external voltage source greater than the lnbh25s nominal v out and for a time longer than i sink_time - out (10 ms typ.), pdo i2c bit is set to 1. this may happen due to an external voltage source on the lnb output (vout pin). for current threshold and deglitch time details, see table 13: "electrical characteristics" . 2.16 power - on i2c interface reset and undervoltage lockout the i2c interface, built into the lnbh25s, is automatically reset at power - on. as long as the v cc is below the undervoltage lockout (uvlo) threshold (4.7 v typ.), the interface does not respond to any i2c command and all data register bits are initialized to zero, therefore the power blocks are disabled. once v cc rises above 4.8 v typ. the i2c interface becomes operative and data registers can be configured by the main microprocessor. 2.17 png (input voltage minimum detection) when input voltage (vcc pin) is lower than lpd (low power diagnostic) minimum thresholds, the png i2c bit is set to 1 and the flt pin is set low. see table 13: "electrical characteristics" for threshold details. 2.18 isw (inductor switching curr ent limit) in order to allow low saturation current inductors to be used, the maximum dc - dc inductor switching current limit threshold can be set by one i2c bit (isw). two values are available: 2.5 a typ. (with isw = 1) and 4 a typ. (with isw = 0). 2.19 comp (boost capacitors and inductor) the dc - dc conv erter compensation loop can be optimized to properly work with both ceramic and electrolytic capacitors (vup pin). for this purpose, one i2c bit in the data 4 register, see comp table 10: "data 4 (read/write register. regist er address = 0x5)" can be set to 1 or 0 as follows: ? comp = 0 for electrolytic capacitors ? comp = 1 for ceramic capacitors for recommended dc - dc capacitor and inductor values see section 5: "typical application circuits" and the bom in and table 6: "diseqc 2.x bill of material" .
application information lnbh25s 12 / 37 docid026736 rev 2 2.20 olf (over current and short - circuit protection and diagnostic) to reduce the total power dissipation during an overload or a short - circu it condition, the device is provided with a dynamic short - circuit protection. it is possible to set the short - circuit current protection either statically (simple current clamp) or dynamically by the pcl bit of i2c data 3 register. when the pcl (pulsed cur rent limiting) bit is set low, the overcurrent protection circuit works dynamically: as soon as an overload is detected, the output current is provided for t on time (90 ms or 180 ms typ., according to the timer bit programmed in the data 3 register) and af ter that, the output is set in shutdown for t off time of typically 900 ms. simultaneously, the diagnostic olf i2c bit of the system register is set to 1 and the flt pin is set to low level. after this time has elapsed, the output is resumed for a time t o n . at the end of t on , if the overload is still detected, the protection circuit cycles again through t off and t on . at the end of a full t on in which no overload is detected, normal operation is resumed and the olf diagnostic bit is reset to low after a reg ister reading. typical t on +t off time is 990 ms (if timer=0) or 1080 ms (if timer=1) and it is determined by an internal timer. this dynamic operation can reduce the power dissipation in short - circuit condition, assuring excellent power - on startup in most conditions. however, there may be some cases in which a highly capacitive load on the output may cause a difficult startup when the dynamic protection is chosen. this can be solved by initiating any power startup in static mode (pcl=1) and, then, switching to the dynamic mode (pcl=0) after a specified period of time depending on the output capacitance. also , in static mode, the diagnostic olf bit goes to 1 (and the flt pin is set to low) when the current clamp limit is reached and returns low when the ove rload condition is cleared and register reading is performed. after the overload condition is removed, normal operation can be resumed in two ways, according to the olr i2c bit on the data 4 register. if olr=1, all vsel 1..4 bits are reset to 0 and lnb o utput (vout pin) is disabled. to re - enable the output stage, vsel bits have to be set again by the microprocessor, and the olf bit is reset to 0 after a register reading operation. if olr=0, output is automatically re - enabled as soon as the overload cond ition is removed, and the olf bit is reset to 0 after a register reading operation. 2.21 otf (thermal protection and diagnostic) the lnbh25s is also pr otected against overheating: when the junction temperature exceeds 150 c (typ.), the step - up converter and the linear regulator shut off, the diagnostic otf bit in the status 1 register is set to 1 and the flt pin is set to low level. after the overtemp erature condition is removed, normal operation can be resumed in two ways, according to the therm i2c bit on the data 4 register. if therm=1, all vsel 1..4 bits are reset to 0 and lnb output (vout pin) is disabled. to re - enable the output stage, vsel bit s must be set again by the microprocessor, while the otf bit is reset to 0 after a register reading operation. if therm=0, output is automatically re - enabled as soon as the overtemperature condition is removed, while the otf bit is reset to 0 after a r egister reading operation.
lnbh25s pin configur ation docid026736 rev 2 13 / 37 3 pin configuration figure 5 : pin connection (top view) table 2: pin description pin symbol name pin function 2 flt f lt open drain output for ic fault conditions. it is set low in case of overload (olf bit) or overheating status (otf bit) or power not good (png) is detected. to be connected to pull - up resistor (5 v max.) 3 lx nmos drain integrated n - channel power mosfet drain 4 pgnd power ground dc - dc converter power ground. to be connected directly to exposed pad 6 addr address setting two i2c bus addresses available by setting the address pin level voltage. see table 16: "address pin c haracteristics" 7 scl serial clock clock from i2c bus 8 sda serial data bi - directional data from/to i2c bus 9 isel current selection the resistor rsel connected between isel and gnd defines the linear regulator current limit threshold. refer to section 2.6: "output current limit selection" and iset bit description in table 9: "data 3 (read/write register. register address = 0x4)" 15 gnd analog ground analog circuit ground. to be connec ted directly to the exposed pad 16 vbyp bypass capacitor needed for internal pre - regulator filtering. the vbyp pin connects an external ceramic capacitor. any connection of this pin to external current or voltage sources may cause permanent damage to the device d s qo u t d s qi n / ex t m v u p d e t i n n c v o u t a dd r 1 2 3 4 5 6 1 8 1 7 1 6 1 5 1 4 1 3 7 8 9 1 2 1 1 1 0 1 9 2 0 2 1 2 2 2 3 2 4 g n d n c v c c p g n d f l t n c l x s d a i se l n c n c n c n c vby p bps w n c s c l 1 2 3 4 5 6 1 8 1 7 1 6 1 5 1 4 1 3 7 8 9 1 2 1 1 1 0 1 9 2 0 2 1 2 2 2 3 2 4 gipg0907141409lm
pin configuration lnbh25s 14 / 37 docid026736 rev 2 pin symbol name pin function 17 vcc supply input 8 to 16 v ic dc - dc power supply 18 bpsw switch control to be connected to an external transistor to be used to bypass the output rl filter needed in diseqc 2.x applications during diseqc transmitting mode, see section 5: "typical application circuits" . set to ground if it is not used. open drain pin 19 detin tone detector input 22 khz tone decoder input open drain pin has to be ac coupled to the diseqc 2.0 bus. set to ground if it is not used 2 0 vout lnb output port output of the integrated very low drop linear regulator. see table 14: "output voltage selection table (data1 register, write mode)" for voltage selections and description 21 vup step - up voltage inpu t of the linear post - regulator. the voltage on this pin is monitored by the internal step - up controller to keep a minimum dropout across the linear pass transistor 22 dsqin dsqin for diseqc envelope input or external 22 khz ttl input it can be used as dis eqc envelope input or external 22 khz ttl input depending on extm i2c bit setting as follows: extm=0, ten=1. it accepts the diseqc envelope code from the main microcontroller. the lnbh25s uses this code to modulate the internally generated 22 khz carrier. if extm=ten=1. it accepts external 22 khz logic signals which activate the 22 khz tone output, refer to section 2.3: "data encoding by external diseqc envelope control through the dsqin pin" . pull - up high if the tone output is activated by the ten i2c bit only 23 dsqout diseqc output open drain output of the tone detector to the main microcontroller for diseqc 2.0 data decoding. it is low when tone is detected to the detin input pin. set to ground if it is not used epad ep ad exposed pad to be connected with power ground and to the ground layer through vias to dissipate heat 1, 5, 10, 11, 12, 13, 14, 24 nc not internally connected not internally connected. these pins can be connected to gnd to improve thermal performance
lnbh25s maximum ratings docid026736 rev 2 15 / 37 4 maximum ratings table 3: absolute maximum ratings symbol parameter value unit v cc dc power supply input voltage pins - 0.3 to 20 v v up dc input voltage - 0.3 to 40 v i out o utput current internally limited ma v out dc output pin voltage - 0.3 to 40 v v i logic input pin voltage (sda, scl, dsqin, addr pins) - 0.3 to 7 v v o logic output pin voltage (flt, dsqout) - 0.3 to 7 v v bpsw bpsw pin voltage - 0.3 to 40 v v detin detector i nput signal amplitude - 0.6 to 2 v i o logic output pin current (flt, dsqout, bpsw) 10 ma lx lx input voltage - 0.3 to 30 v v byp internal reference pin voltage - 0.3 to 4.6 v isel current selection pin voltage - 0.3 to 3.5 v t stg storage temperature range - 50 to 150 c t j operating junction temperature range - 25 to 125 c esd esd rating with human body model (hbm) all pins, unless power output pins 2 kv esd rating with human body model (hbm) for power output pins 4 table 4: thermal data symbol parame ter value unit r thjc thermal resistance junction - case 2 c/w r thja thermal resistance junction - ambient with the device soldered on 2s2p 4 - layer pcb provided with thermal vias below exposed pad 40 c/w absolute maximum ratings are those values beyond which damage to the device may occur. these are stress ratings only and functional operation of the device at these conditions is not implied. exposure to absolute maximum - rated conditions for extended periods may affect the device reliability. all voltag e values are referred to network ground terminal.
typical application circuits lnbh25s 16 / 37 docid026736 rev 2 5 typical application circuits figure 6 : diseqc 1.x application circuit table 5: di seqc 1.x bill of material component notes r1 (rsel) smd resistor. refer to table 13: "electrical characteristics" and isel pin description in table 2: "pin description" c1 > 25 v electroly tic capacitor, 100 f or higher is suitable or > 25 v ceramic capacitor, 10 f or higher is suitable c2 with comp = 0, > 25 v electrolytic capacitor, 100 f or higher is suitable or with comp = 1, > 35 v ceramic capacitor, 22 f (or 2 x 10 f) or higher i s suitable c3 from 470 nf to 2.2 f ceramic capacitor placed as closer as possible to vup pins. higher values allow lower dc - dc noise c5 from 100 nf to 220 nf ceramic capacitor placed as close as possible to vout pins. higher values allow lower dc - dc noi se c4, c7 220 nf ceramic capacitors. to be placed as close as possible to vout pin d1 stps130a or similar schottky diode d2 1n4001 - 07, s1a - s1m, or any similar general purpose rectifier d3 bat54, bat43, 1n5818, or any low power schottky diode with i f (av ) > 0.2 a, v rrm > 25 v, v f < 0.5 v. to be placed as close as possible to vout pin
lnbh25s typical application circuits docid026736 rev 2 17 / 37 component notes l1 with comp=0, use 10 h inductor with i sat > i peak where i peak is the boost converter peak current, or with comp=1 and c2 = 22 f, use 6.8 h inductor with i sat > i peak wh ere i peak is the boost converter peak current figure 7 : diseqc 2.x application circuit table 6: diseqc 2.x bill of material component notes r1 (rsel) smd resistor. refer to table 13: "electrica l characteristics" and isel pin description in table 2: "pin description" c1 > 25 v electrolytic capacitor, 100 f or higher is suitable or > 25 v ceramic capacitor, 10 f or higher is suitable c2 with comp = 0, > 25 v e lectrolytic capacitor, 100 f or higher is suitable or with comp = 1, > 35 v ceramic capacitor, 22 f (or 2 x10 f) or higher is suitable c3 from 470 nf to 2.2 f ceramic capacitor placed as closer as possible to vup pin. higher values allow lower dc - dc n oise c5 from 100 nf to 220 nf ceramic capacitor placed as closer as possible to vout pin. higher values allow lower dc - dc noise c4, c7 220 nf ceramic capacitors. to be placed as closer as possible to vout pin c6 10 nf ceramic capacitors d1 stps130a or similar schottky diode
typical application circuits lnbh25s 18 / 37 docid026736 rev 2 component notes d2 1n4001 - 07, s1a - s1m, or any similar general purpose rectifier d3 bat54, bat43, 1n5818, or any low power schottky diode with i f (av) > 0.2 a, v rrm > 25 v, v f < 0.5 v. to be placed as closer as possible to vout pin l1 with comp = 0 , use 10 h inductor with i sat > i peak where i peak is the boost converter peak current or with comp=1 and c2 = 22 f, use 6.8 h inductor with i sat > i peak where i peak is the boost converter peak current l2 220 h - 270 h inductor as per diseqc 2.x speci fication tr1 mmbta92, 2str2160 or any low power pnp with i c > 250 ma, v ce > 30 v, can b e used also any small power pmos with i d > 250 ma, r ds(on) < 0.5 w, v ds > 20 v, can be used
lnbh25s i2c bus interface docid026736 rev 2 19 / 37 6 i2c bus interface data transmission from the main microprocessor to the lnbh25s and vice versa takes place through the 2 - wire i2c bus interface, consisting of the 2 - line sda and scl (pull - up resistors to positive supply voltage must be external ly connected). 6.1 data validity as shown in figure 8: "data validity on the i2c bus" , the data on the sda line must be stable during the high s emi - period of the clock. the high and low state of the data line can only change when the clock signal on the scl line is low. 6.2 start and stop condition as shown i n figure 9: "timing diagram of i2c bus" , a start condition is a transition from high to low of the sda line while scl is high. the stop condition is a transition from low to high of the sda line while scl is high. a stop co ndition must be sent before each start condition. 6.3 byte format every byte transferred to the sda line must contain 8 bits. each byte must be followed by an acknowledge bit. the msb is the first to be transferred. 6.4 acknowledge the master (microprocessor) puts a resistive high level on the sda line during the acknowledge clock pulse, see figure 10: "acknowledge on the i2c bus" . the peripheral (lnbh25s), which acknowledges, must pull down (low) the sda line during the acknowledge clock pulse, so that the sda line is stable low during this clock pulse. the peripheral, whic h has been addressed, has to generate acknowledge after the reception of each byte, otherwise the sda line remains at high level during the nin th clock pulse time. in this case, the master transmitter can generate the stop information in order to abort the transfer. the lnbh25s doesnt generate acknowledge if the v cc supply is below the undervoltage lockout threshold (4.7 v typ.). 6.5 transmission without acknowledge if the detection of the lnbh25s acknowledges is not necessary, the microprocessor can use a simpler transmission: it simply waits for one clock without checking the slave acknowledging, and sends the new data. this approach is less protected from mi sworking and decreases noise immunity.
i2c bus interface lnbh25s 20 / 37 docid026736 rev 2 figure 8 : data validity on the i2c bus figure 9 : timing diagram of i2c bus figure 10 : acknowledge on the i2c bus
lnbh25s i2c interface protocol docid026736 rev 2 21 / 37 7 i2c interface protoc ol 7.1 write mode transmission the lnbh25s interface protocol is made up of: ? a start condition (s) ? a chip address byte with the lsb bit r/w = 0 ? a register address (internal address of the first register to be accessed) ? a sequence of data (byte to write to the addressed internal register + acknowledge) ? the following bytes, if an y, to be written to successive internal registers ? a stop condition (p). the transfer lasts until a stop bit is encountered ? the lnbh25s, as slave, acknowledges every byte transfer figure 11 : example of writing procedure starting with first data address 0x2 ack = acknowledge s = start p = stop r/w = 1/0, read/write bit x = 0/1, set the values to select the chip address, see table 16: "address pin characteristics" for pin selection and to select th e register address, see table 7: "data 1 (read/write register. register address = 0x2)" . the writing procedure can start from any register address by simply setting x values in the register address byte (after the chip a ddress). it can be also stopped by the master by sending a stop condition after any acknowledge bit. s x x a c k 0 0 x 0 0 0 x r /w = 0 0 0 1 0 0 0 s x x a c k 0 0 x 0 0 0 x r /w = 0 a c k 0 1 0 0 0 vs e l 1 vs e l 3 vs e l 2 n / a n / a n / a vs e l 4 n / a a c k m s b l s b c h i p ad d r e ss m s b l s b r e g i s t e r ad d r e ss m s b l s b c h i p ad d r e ss m s b l s b r e g i s t e r ad d r e ss l p m n/a t en ex t m n / a n / a n / a n / a a c k i set i sw p c l n / a n / a n / a t i m er n / a a c k en_imon olr p a c k n / a n / a n / a n / a t h e r m c o m p p m sb l sb m sb l sb m sb l sb m sb l sb d a t a 1 a d d = 0 x 2 d a t a 2 a d d = 0 x 3 d a t a 3 a d d = 0 x 4 d a t a 4 a d d = 0 x 5 m sb l sb m sb l sb m sb l sb m sb l sb d a t a 1 a d d = 0 x 2 d a t a 2 a d d = 0 x 3 d a t a 3 a d d = 0 x 4 d a t a 4 a d d = 0 x 5 gipg1007141414lm
i2c interface protocol lnbh25s 22 / 37 docid026736 rev 2 7.2 read mode transmission in read mode the byte sequence as fo llows: ? a start condition (s) ? a chip address byte with the lsb bit r/w=0 ? the register address byte of the internal first register to be accessed ? a stop condition (p) ? a new master transmission with the chip address byte and the lsb bit r/w=1 ? after the a cknowledge, the lnbh25s starts to send the addressed register content. as long as the master keeps the acknowledge low, the lnbh25s transmits the next address register byte content ? the transmission is terminated when the master sets the acknowledge high w ith the following stop bit figure 12 : example of reading procedure starting with first status address 0x0 ack = acknowledge s = start p = stop r/w = 1/0, read/write bit x = 0/1, set the values to select the chip address, see table 16: "address pin characteristics" for pin selection and to select the register address see table 7: "data 1 (read/write register. register address = 0x2)" .
lnbh25s i2c interface protocol docid026736 rev 2 23 / 37 the writing procedure can st art from any register address (status 1,2 or data 1..4) by simply setting x values in the register address byte (after the chip address). it can be also stopped by the master by sending a stop condition after any acknowledge bit. 7.3 data registers the data 1..4 registers can be addressed both to write and read mode. in read mode they return the last writing byte status received in the previous write transmission. the followin g tables provide the register address values of data 1..4 and a function description of each bit. table 7: data 1 (read/write register. register address = 0x2) bit name value description bit 0 (lsb) vsel1 0/1 output voltage selection bits. refer to table 14: "output voltage selection table (data1 register, write mode)" bit 1 vsel2 0/1 bit 2 vsel3 0/1 bit 3 vsel4 0/1 bit 4 n/a 0 reserved. keep to 0 bit 5 n/a 0 reserved. keep to 0 bit 6 n/a 0 reserved. keep to 0 bit 7 (msb) n/a 0 reserved. keep to 0 n/a = reserved bit all bits reset to 0 at power - on table 8: data 2 (read/write register. register address = 0x3) bit name value description bit 0 (lsb) ten 1 22 khz tone enabled. tone output controlled by dsq in pin 0 22 khz tone output disabled bit 1 lpm 1 low power mode active (used with 22 khz tone output disabled only) 0 low power mode deactivated (keep always lpm = 0 during 22 khz tone transmission) bit 2 extm 1 dsqin input pin is set to receive ex ternal 22 khz ttl signal source 0 dsqin input pin is set to receive external diseqc envelope ttl signal bit 3 n/a 0 reserved. keep to 0 bit 4 n/a 0 reserved. keep to 0 bit 5 n/a 0 reserved. keep to 0 bit 6 n/a 0 reserved. keep to 0 bit 7(ms b) n/a 0 reserved. keep to 0
i2c interface protocol lnbh25s 24 / 37 docid026736 rev 2 n/a = reserved bit all bits reset to 0 at power - on table 9: data 3 (read/write register. register address = 0x4) bit name value description bit 0 (lsb) iset 1 current limit of lnb output (vout pin) set to lower current ran ge (see section 2.6: "output current limit selection" ) 0 current limit of lnb output (vout pin) set to default range (see section 2.6: "output current limit selection" ) bit 1 isw 1 dc - dc , inductor switching current limit set to 2.5 a typ. 0 dc - dc, inductor switching current limit set to 4 a typ. bit 2 pcl 1 pulsed (dynamic) lnb output current limiting is deactivated 0 pulsed (dynamic) lnb output current limiting is active bit 3 ti mer 1 pulsed (dynamic) lnb output current t on time set to 180 ms typ. 0 pulsed (dynamic) lnb output current t on time set to 90 ms typ. bit 4 n/a 0 reserved. keep to 0 bit 5 n/a 0 reserved. keep to 0 bit 6 n/a 0 reserved. keep to 0 bit 7(msb) n /a 0 reserved. keep to 0 n/a = reserved bit all bits reset to 0 at power - on table 10: data 4 (read/write register. register address = 0x5) bit name value description bit 0 (lsb) en_imon 1 imon diagnostic function is enabled. (v out is set to 21 v typ.) 0 imon diagnostic function is disabled, keep always at 0 if imon is not used bit 1 n/a - reserved bit 2 n/a - reserved bit 3 olr 1 in case of overload protection activation (olf=1), all vsel 1..4 bits are reset to 0 and lnb output (vout pin) is disabled. vsel bits have to be set again by the master after the overcurrent condition is removed (olf=0) 0 in case of overload protection activation (olf=1) the lnb output (vout pin) is automatically enabled as soon as the overload condition is removed (olf=0) with the previous vsel bits setting bit 4 n/a - reserved bit 5 n/a - reserved
lnbh25s i2c interface protocol docid026736 rev 2 25 / 37 bit name value description bit 6 therm 1 if thermal protection is active (otf=1), all vsel 1..4 bits are reset to 0 and lnb output (vout pin) is disabled. vsel bits have to be set again by th e master after the overtemperature condition is removed (otf=0) 0 if thermal protection is active (otf=1) the lnb output (vout pin) is automatically enabled as soon as the overtemperature condition is removed (otf=0) with the previous vsel bits setting bit 7(msb) comp 1 dc - dc converter compensation: set to use very low esr capacitors or ceramic caps on vup pin 0 dc - dc converter compensation: set to use standard electrolytic capacitors on vup pin n/a = reserved bit all bits reset to 0 at power - on
i2c interface protocol lnbh25s 26 / 37 docid026736 rev 2 7.4 status registers status 1, 2 registers can be only addressed to read mode and provide the diagnostic functions described in the following tables. table 11: status 1 (read register. register address = 0x0) bit name value description bit 0 (lsb) olf 1 vout pin overload protection has been triggered (i out > i lim ). refer to table 9: "data 3 (read/write register. register address = 0x4)" for th e overload operation settings (iset, pcl, timer bits) 0 no overload protection has been triggered to the vout pin (i out < i lim ) bit 1 n/a - reserved bit 2 vmon 1 output voltage (vout pin) lower than vmon specification thresholds. refer to table 17: "output voltage diagnostic (vmon bit, status 1 register) characteristics" 0 output voltage (vout pin) is within the vmon specifications bit 3 n/a - reserved bit 4 pdo 1 overcurrent detected on output pull - down stage for a time longer than the deglitch period. this may happen due to an external voltage source present on the lnb output (vout pin) 0 no overcurrent detected on output pull - down stage bit 5 n/a - reserved bit 6 otf 1 junction overtemperature is detected, t j > 150 c. see also therm bit setting in table 10: "data 4 (read/write register. register address = 0x5)" 0 junction overtemperature is not detected, t j < 135 c. t j is below thermal protection threshold bit 7 (msb) pn g 1 input voltage (vcc pin) lower than lpd minimum thresholds. refer to table 13: "electrical characteristics" 0 input voltage (vcc pin) higher than lpd thresholds. refer to table 13: "ele ctrical characteristics" n/a = reserved bit all bits reset to 0 at power - on
lnbh25s i2c interface protocol docid026736 rev 2 27 / 37 table 12: status 2 (read register. register address = 0x1) bit name value description bit 0 (lsb) tdet 1 22 khz tone presence is detected on the detin pin 0 no 22 khz tone is detected on the detin pin bit 1 n/a - reserved bit 2 tmon 1 22 khz tone present on the detin pin is out of tmon specification threshold: the tone frequency or the a tone (tone amplitude) is out of the thresholds guaranteed in the tmon electrical chara cteristics 0 22 khz tone present on the detin pin is within tmon specification thresholds. refer to table 19: "22 khz tone diagnostic (tmon bit, status 2 register) characteristics" bit 3 n/a - reserved bit 4 imon 1 out put current (from vout pin) is lower than imon specification thresholds 0 output current (from vout pin) is higher than imon speci fications bit 5 n/a - reserved bit 6 n/a - reserved bit 7(msb) n/a - reserved n/a = reserved bit all bits reset to 0 a t power - on
electrical characteristics lnbh25s 28 / 37 docid026736 rev 2 8 electrical characteristics see section 5: "typical application circuits" , t j from 0 to 85 c, all data 1..4 register b its set to 0 unless vsel1 = 1, rsel = 11.5 k, dsqin = low, v in = 12 v, i out = 50 ma, unless otherwise stated. typical values are referred to t j = 25 c. v out = vout pin voltage. see section 6: "i2c bus interface" and section 7: "i2c interface protocol" . table 13: electrical characteristics symbol parameter test conditions min. typ. max. unit v in supply voltage (1) 8 12 16 v i in supply current i out = 0 ma 6 ma 22 khz tone enabled (ten=1), dsqin = high, i out = 0 ma 10 ma vsel1=vsel2=vsel3=vse l4=0 1 ma v out output voltage total accuracy valid at any v out selected level - 3.5 +3.5 % v out line regulation v in = 8 to 16 v 40 mv v out load regulation i out from 50 to 750 ma 100 i lim output current limiting thresholds rsel = 11.5 k, iset = 0 750 1100 ma rsel = 16.2 k, iset = 0 500 750 rsel = 22 k, iset = 0 350 550 i lim output current limiting thresholds rsel = 11.5 k, iset = 1 500 ma rsel = 16.2 k, iset = 1 350 rsel = 22 k, iset = 1 250 i sc output short - circuit current rsel = 11.5 k, iset = 0 500 ma ss soft - start time v out from 0 to 13 v 4 ms ss soft - start time v out from 0 to 18 v 6 ms t13 - 18 soft transition rise time v out from 13 to 18 v 1.5 ms t18 - 13 soft transition fall time v out from 18 to 13 v 1.5 ms t off dynamic overload protection off - time pcl = 0, output shorted 900 ms t on dynamic overload protection on - time pcl = timer = 0, output shorted t off /1 0 pcl = 0, timer = 1, output shorted t off /5 a tone tone amplitude dsqin = high, extm=0, ten=1 i out from 0 to 750 ma c bus from 0 to 750 nf 0.55 0.675 0.8 v pp f tone tone frequency dsqin = high, extm=0, ten=1 20 22 24 khz d tone tone duty cycle 43 50 57 % tr, tf tone rise or fall time (2) 5 8 15 s
lnbh25s electrical characteristics docid026736 rev 2 29 / 37 symbol parameter test conditions min. typ. max. unit eff dc/dc dc - dc converter efficiency i out = 500 ma 93 % f sw dc - dc converter switching frequency 440 khz uvlo undervoltage lockout thresholds uvlo threshold risin g 4.8 v uvlo threshold falling 4.7 v lp low power diagnostic (lpd) thresholds v lp threshold rising 7.2 v v lp threshold falling 6.7 v il dsqin, pin logic low 0.8 v v ih dsqin, pin logic high 2 v i ih dsqin, pin input current v ih = 5 v 15 a f detin tone detector frequency capture range (3) 0.4 v pp sine wave 19 22 25 khz v detin tone detector input amplitude (3) sine wave signal, 22 khz 0.3 1.5 v pp z detin tone detector input impedance 150 k v ol_b ps w bpsw pin low voltage i ol_bpsw = 5 ma, dsqin = high, extm=0, ten=1 0.7 v v ol dsqout, flt pins logic low detin tone present, i ol = 2 ma 0.3 0.5 v i oz dsqout, flt pins leakage current detin tone absent, v oh = 6 v 10 a i obk output backward current all vselx=0, v obk = 30 v - 3 - 6 ma i sink output low - side sink current v out forced at v out_nom + 0.1 v 70 ma i sink_ time - out low - side sink current time - out v out forced at v out_nom + 0.1 v pdo i2c bit is set to 1 after this time is elapsed 10 ms i re v max. reverse current v out forced at v out_nom + 0.1 v after pdo bit is set to 1 (i sink_time - out elapsed) 2 ma t shdn thermal shutdown threshold 150 c dt shdn thermal shutdown hysteresis 15 c notes: (1) in applications where (v cc - v out ) > 1.3 v the increased power dissipation inside the integrated ldo must be taken into account in the application thermal management design. (2) guaranteed by design. (3) frequency range in which the detin function is guaranteed. the v pp level is intended on the lnb bus (before the c6 capacitor. see typical application circuit for diseqc 2.x). i out from 0 to 750 ma, c bus from 0 to 750 nf.
electrica l characteristics lnbh25s 30 / 37 docid026736 rev 2 table 14: output voltage selection table (data1 register, write mode) vsel4 vsel3 vsel2 vsel1 v out min. v out voltage v out max. fu nction 0 0 0 0 0.000 v out disabled. the lnbh25s is set in standby mode 0 0 0 1 12.545 13.000 13.455 0 0 1 0 12.867 13.333 13.800 0 0 1 1 13.188 13.667 14.145 0 1 0 0 13.51 14.000 14.490 0 1 0 1 13.832 14.333 14.835 0 1 1 0 14.153 14.667 15.18 0 0 1 1 1 14.475 15.000 15.525 1 0 0 0 17.515 18.150 18.785 1 0 0 1 17.836 18.483 19.130 1 0 1 0 18.158 18.817 19.475 1 0 1 1 18.48 19.150 19.820 1 1 0 0 18.801 19.483 20.165 1 1 0 1 19.123 19.817 20.510 1 1 1 0 19.445 20.150 20.855 1 1 1 1 19.766 20.483 21.200 t j from 0 to 85 c, v i = 12 v table 15: i2c electrical characteristics symbol parameter test conditions min. typ. max. unit v il low level input voltage sda, scl 0.8 v v ih high level input voltage sda, scl 2 v i in input cur rent sda, scl, v in = 0.4 to 4.5 v - 10 10 a v ol low level output voltage a sda (open drain), i ol = 6 ma 0.6 v f max maximum clock frequency scl 400 khz t j from 0 to 85 c, v i = 12 v table 16: address pin characteristics symbol parameter test condit ions min. typ. max. unit v addr - 1 0001000(r/w) address pin voltage range r/w bit determines the transmission mode: read (r/w=1) write (r/w=0) 0 0.8 v v addr - 2 0001001(r/w) address pin voltage range r/w bit determines the transmission mode: read (r/w=1 ) write (r/w=0) 2 5 v a guaranteed by design.
lnbh25s electrical characteristics docid026736 rev 2 31 / 37 refer to section 5: "typical application circuits" , t j from 0 to 85 c, all dat 1..4 register bits set to 0, rsel = 11.5 k, dsqin = low, v in = 12 v, i out = 50 ma, unless otherwise stated. typical values are referred to t j = 25 c. v out = vout pin voltage. see section 6: "i2c bus interface" and section 7: "i2c interface protocol" . table 17: output voltage diagnostic (vmon bit, status 1 register) characteristics symbol parameter test conditions min. typ. max. unit v th - l diagnostic low threshold at v out = 13.0 v vsel1 =1, vsel2 = vsel3 = vsel4 = 0 80 90 95 % v th - l diagnostic low threshold at v out = 18.15 v vsel4 =1, vsel1 = vsel2 = vs el3 = 0 80 90 95 % if the output voltage is lower than the min. value, the vmon i2c bit is set to 1. if vmon=0 then v out > 80% of v out typical if vmon=1 then v out < 95% of v out typical refer to section 5: "typical app lication circuits" , t j from 0 to 85 c, rsel = 11.5 k, dsqin = low, v in = 12 v, unless otherwise stated. typical values are referred to t j = 25 c. v out = vout pin voltage. see section 6: "i2c bus interface" and section 7: "i2c interface protocol" . table 18: output current diagnostic (imon bit, status 2 register) characteristics symbol parameter test conditions min. typ. max. unit i th minimum current diagnostic threshold en_imon = 1 (v out is set to 21 v typ.) 5 12 20 ma if the output current is lower than the min. threshold limit, the imon i2c bit is set to 1. if the output current is higher than the max. threshold limit, the imon i2c bit is set to 0.
electrical characteristics lnbh25s 32 / 37 docid026736 rev 2 refer to section 5: " typical application circuits" , t j from 0 to 85 c, all data 1..4 register bits set to 0 unless vsel1 = 1, ten =1, rsel = 11.5 k, dsqin = high, v in = 12 v, i out =50 ma, unless otherwise stated. typical values are referred to t j = 25 c. v out = vout pin v oltage. see section 6: "i2c bus interface" and section 7: "i2c interface protocol" . table 19: 22 khz tone diagnostic (tmon bit, status 2 register) characteristics symbol parameter test condi tions min. typ. max. unit a th - l amplitude diagnostic low threshold detin pin ac coupled 200 300 400 mv a th - h amplitude diagnostic high threshold detin pin ac coupled 900 1100 1200 mv f th - l frequency diagnostic low thresholds detin pin ac coupled 13 16.5 20 khz f th - h frequency diagnostic high thresholds detin pin ac coupled 24 29.5 38 khz if the 22 khz tone parameters are lower or higher than the above limits, the tmon i2c bit is set to 1.
lnbh25s package information docid026736 rev 2 33 / 37 9 package information in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack specifications, grade defini tions and product status are available at: www.st.com. ecopack is an st trademark.
package inform ation lnbh25s 34 / 37 docid026736 rev 2 9.1 qfn24l (4x4 mm) package information figure 13 : qf n24l (4x4 mm) package outline
lnbh25s package information docid026736 rev 2 35 / 37 table 20: qfn24l (4x4 mm) mechanical data dim. mm min. typ. max. a 0.80 0.90 1.00 a1 0.00 0.02 0.05 b 0.18 0.25 0.30 d 3.90 4.00 4.10 d2 2.55 2.70 2.80 e 3.90 4.00 4.10 e2 2.55 2.70 2.80 e 0.45 0.50 0.55 l 0.25 0.35 0.40 figure 14 : qfn24l (4x4 mm) recommended footprint
revision history lnbh25s 36 / 37 docid026736 rev 2 10 revision history table 21: document revision history date revision changes 23 - jul - 2014 1 initial release. 24 - mar - 2015 2 updated section 2.6, figure 5 and table 13 .
lnbh25s docid026736 rev 2 37 / 37 important notice C please read carefully stmicroelectronics nv and its subsidiaries (s t) reserve the right to make changes, corrections, enhancements, modifications, and improvements to st products and/or to this document at any time without notice. purchasers should obtain the latest relevant information on st products before placing orde rs. st products are sold pursuant to sts terms and conditions of sale in place at the time of order acknowledgement. purchasers are solely responsible for the choice, selection, and use of st products and st assumes no liability for applicati on assista nce or the design of purchasers products. no license, express or implied, to any intellectual property right is granted by st herein. resale of st products with provisions different from the information set forth herein shall void any warranty granted by st for such product. st and the st logo are trademarks of st. all other product or service names are the property of their respective owners. information in this document supersedes and replaces information previously supplied in any prior versions of this document. ? 2015 stmicroelectronics C all rights reserved

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